Systems composed of multiple but coordinated processors were first developed and used in the context of mainframes. More recently, interest in multiple processor systems has increased as a consequence of the low cost and high performance of microprocessors, with the objective of replicating mainframe performance through the parallel use of multiple microprocessors.
A variety of architectures have been defined for multiprocessor systems. Most designs rely upon highly integrated architectures by virtue of the need for cache coherence. In such systems, cache coherence is maintained through complex logic circuit interconnection to cache memories associated with the individual microprocessors to ensure data consistency as reflected in the various caches in main memory.
One problem that exists with these highly integrated architectures is the initializing or booting of the multiprocessor system as the system is turned on. Various techniques have been utilized to handle this initial coordination of the multiprocessors during boot. Some systems dedicate a surface or auxiliary processor for this management process during boot. That is, a specialized processor or hardware is utilized for testing system memory and coordinating the booting of each of the processors. However, this dedicated service processor or hardware is either not utilized or is underutilized after system boot. In addition, should the dedicated service processor or hardware fail for some reason, then the whole system cannot boot as a result.
Another approach has been to use multiple copies of the boot code, one for each processor. Each processor boots itself and one of the processors has additional boot code for booting the system configuration. However, this requires large amount of ROM for storing multiple copies of the boot code. In addition, should the processor responsible for booting the system fail for some reason, then the system cannot boot as a result. One example of this approach is disclosed in "Apparatus and Method for Booting a Multiple Processor System Having a Global/Local Memory Architecture", U.S. Pat. No. 5,448,716, filed Oct. 30, 1992, hereby incorporated by reference. One main disadvantage to this approach is that separately stored copies of the boot code are provided to each processor, whether or not that processor utilizes that boot code.